A power semiconductor transistor, like an insulated-gate bipolar transistor (IGBT), may comprise a vertical metal-oxide-semiconductor (MOS)-structure with a vertical gate trench extending into a drift region of the power semiconductor transistor. Further, an oxide layer may be formed in the vertical gate trench.
Due to its geometrics a bottom of the vertical gate trench may be exposed to high electric field strengths during an operation of the power semiconductor transistor. Thereby, an undesired high feedback capacitance may be generated. Further, a premature aging of the oxide layer, in particular at the bottom of the vertical gate trench, may be promoted due to the exposure to high electric field strengths.
To reduce the electric field strength at the bottom of the vertical gate trench a thickness of the oxide layer at the bottom of the vertical gate trench may be increased. Such an oxide layer may be formed by an imprecise timed oxide etching process combined with a structured etch mask. Further, an increase of a thickness of the oxide layer in an upper portion of the vertical gate trench, e.g. in a channel region of the power semiconductor transistor, may result in an undesired increase of a threshold voltage of the power semiconductor transistor.
Alternatively, a shield electrode may be formed at the bottom of the vertical gate trench to reduce the electric field strength at the bottom of the vertical gate trench. Forming a gate trench with a shield electrode may comprise an imprecise times recess etch process of a material of the shield electrode.